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datasheet 5P49V5923 november 11, 2016 1 ?2014 integrated device technology, inc. programmable clock generator 5P49V5923 description the 5P49V5923 is a programmable clock generator intended for high performance consumer, networking, industrial, computing, and data-com munications applications. configurations may be stored in on-chip one-time programmable (otp) memory or changed using i 2 c interface. this is idt?s fifth generation of programmable clock technology (versaclock ? 5). the frequencies are generated from a single reference clock. the reference clock can come from one of the two redundant clock inputs. a glitchless manua l switchover function allows one of the redundant clocks to be selected during normal operation. two select pins allow up to 4 different configurations to be programmed and accessible using processor gpios or bootstrapping. the different selections may be used for different operating modes (full function, partial function, partial power-down), regional standar ds (us, japan, europe) or system production margin testing. the device may be configured to use one of two i 2 c addresses to allow multiple de vices to be used in a system. pin assignment features ? generates up to two independent output frequencies ? high performance, low phase noise pll, <0.7 ps rms typical phase jitter on outputs ? two fractional output dividers (fods) ? independent spread spectrum capability on each output ? four banks of internal non-volatile in-system programmable or factory programmable otp memory ? i 2 c serial programming interface ? three lvcmos outputs, including one reference output ? i/o standards: ? single-ended i/os: 1.8v to 3.3v lvcmos ? input frequency ranges: ? lvcmos reference clock in put (xin/ref) ? 1mhz to 200mhz ? lvds, lvpecl, hcsl differential clock input (clkin, clkinb) ? 1mhz to 200mhz ? crystal frequency range: 8mhz to 40mhz ? output frequency ranges: ? lvcmos clock outputs ? 1mhz to 200mhz ? individually selectable output voltage (1.8v, 2.5v, 3.3v) for each output ? redundant clock inputs with manual switchover ? programmable loop bandwidth ? programmable slew rate control ? programmable crystal load capacitance ? individual output enable/disable ? power-down mode ? 1.8v, 2.5v or 3.3v core v ddd , v dda ? available in 24-pin vfqfpn 4mm x 4mm package ? -40 to +85c industrial temperature operation 1 7 24-pin vfqfpn 19 13 xout xin/ref v dda clkin nc out2 clkinb clksel nc nc v ddo 2 v dda sd/oe sel1/sda sel0/scl v dda nc nc nc out1 v ddo 1 v ddd v ddo 0 out0_sel_i2cb epad gnd 2 3 4 5 6 8 9 10 11 12 14 15 16 17 18 20 21 22 23 24
programmable cloc k generator 2 november 11, 2016 5P49V5923 datasheet functional block diagram applications ? ethernet switch/router ? pci express 1.0/2.0/3.0 ? broadcast video/audio timing ? multi-function printer ? processor and fpga clocking ? any-frequency clock conversion ? msan/dslam/pon ? fiber channel, san ? telecom line cards ? 1 gbe and 10 gbe xin/ref xout clkin clkinb clksel sd/oe sel1/sda sel0/scl v dda v ddd v ddo 0 out0_sel_i2cb v ddo 1 out1 v ddo 2 out2 v dda v dda fod1 fod2 pll otp and control logic
november 11, 2016 3 progra mmable clock generator 5P49V5923 datasheet table 1: pin descriptions number name type description 1 clkin input internal pull-down differential clock input. weak 100kohms internal pull-down. 2 clkinb input internal pull-down complementary differential clock input. weak 100kohms internal pull-down. 3 xout input crystal oscillator interface output. 4 xin/ref input crystal oscillator interface input, or si ngle-ended lvcmos clock input. ensure that the input voltage is 1.2v max.refer to the section ?overdriving the xin/ref interface?. 5v dda power analog functions power supply pin.connect to 1.8v to 3.3v. v dda and v ddd should have the same voltage applied. 6 clksel input internal pull-down input clock select. se lects the active input reference source in manual switchover mode. 0 = xin/ref, xout (default) 1 = clkin, clkinb clksel polarity can be changed by i2 c programming as shown in table 4. 7 sd/oe input internal pull-down enables/disables the outputs (oe) or pow ers down the chip (sd). the sh bit controls the configuration of the sd/oe pin. the sh bit needs to be high for sd/oe pin to be configured as sd. the sp bit (0x02) controls the polarity of the signal to be either active high or low only when pi n is configured as oe (default is active low.) weak internal pull down resistor. when configured as sd, device is shut down and the single-ended lvcmos outputs are driven low. when configured as oe, and outputs are disabled, the outputs can be selected to be tri-stated or driven high/low, depending on the programming bits as shown in the sd/oe pin function truth table. 8 sel1/sda input internal pull-down configuration select pin, or i 2 c sda input as selected by out0_sel_i2cb. weak internal pull down resistor. 9 sel0/scl input internal pull-down configuration select pin, or i 2 c scl input as selected by out0_sel_i2cb. weak internal pull down resistor. 10 v dda power analog functions power supply pin.connect to 1.8v to 3.3v. v dda and v ddd should have the same voltage applied. 11 nc ? no connect. 12 nc ? no connect. 13 nc ? no connect. 14 nc ? no connect. 15 v dda power analog functions power supply pin.connect to 1.8v to 3.3v. v dda and v ddd should have the same voltage applied. 16 nc ? no connect. 17 out2 output output clock 2. please refer to t he output drivers section for more details. 18 v ddo 2 power output power supply. connect to 1.8 to 3.3v. sets output voltage levels for out2. 19 nc ? no connect. 20 out1 output output clock 1. please refer to t he output drivers section for more details. 21 v ddo 1 power output power supply. connect to 1.8 to 3.3v. sets output voltage levels for out1. 22 v ddd power digital functions power supply pin. connect to 1.8 to 3.3v. v dda and v ddd should have the same voltage applied.
programmable cloc k generator 4 november 11, 2016 5P49V5923 datasheet 23 v ddo 0power power supply pin for out0_sel_i2cb. connect to 1.8 to 3.3v. sets output voltage levels for out0. 24 out0_sel_i2cb input/ output internal pull-down latched input/lvcmos output. at power up, the voltage at the pin out0_sel_i2cb is latched by the part and us ed to select the state of pins 8 and 9. if a weak pull up (10kohms) is placed on out0_sel_i2cb, pins 8 and 9 will be configured as hardware select pins, sel1 and sel0. if a weak pull down (10kohms) is placed on out0_sel_i2cb or it is left floating, pins 8 and 9 will act as the sda and scl pins of an i 2 c interface. after power up, the pin acts as a lvcmos reference output. epad gnd gnd connect to ground pad. number name type description
november 11, 2016 5 progra mmable clock generator 5P49V5923 datasheet pll features and descriptions spread spectrum to help reduce electromagnet ic interference (emi), the 5P49V5923 supports spread spectrum modulation. the output clock frequencies can be modulated to spread energy across a broader range of frequencies, lowering system emi. the 5P49V5923 implements spread spectrum using the fractional-n output divide, to achieve controllable modulation rate and spreading magnitude. the spread spectrum can be applied to any output clock, any clock frequency, and any spread amount from 0.25% to 2.5% center spread and -0.5% to -5% down spread. table 2: loop filter pll loop bandwidth range depends on the input reference frequency (fref) and can be set between the loop bandwidth range as shown in the table below. table 3: configuration table this table shows the sel1, sel0 settings to select the configuration stored in otp. four configurations can be stored in otp. these can be factory programmed or user programmed. at power up time, the sel0 and sel1 pins must be tied to either the vddd/vdda power supp ly so that they ramp with that supply or are tied low (thi s is the same as floating the pins). this will cause the regist er configuration to be loaded that is selected according to table 3 above. providing that out0_sel_i2cb was 1 at por an d otp register 0:7=0, after the first 10ms of operation the levels of the selx pins can be changed, either to low or to the same level as vddd/vdda. the selx pins must be driven with a digital signal of < 300ns rise/fall time and only a single pin can be changed at a time. after a pin level change, the device must not be interrupted for at least 1ms so that the new values have time to load and take effect. if out0_sel_i2cb was 0 at por, alternate configurations can only be loaded via the i2c interface. table 4: input clock select input clock select. selects the ac tive input refere nce source in manual switchover mode. 0 = xin/ref, xout (default) 1 = clkin, clkinb clksel polarity can be changed by i 2 c programming as shown in table 4. primsrc is bit 1 of register 0x13. input reference frequency?fref (mhz) loop bandwidth min (khz) loop bandwidth max (khz) 540126 200 300 1000 out0_sel_i2cb @ por sel1 sel0 i 2 c access reg0:7 config 100no00 101no01 110no02 111no03 0 x x yes 1 i2c defaults 0xxyes00 primsrc clksel source 0 0 xin/ref 0 1 clkin, clkinb 1 0 clkin, clkinb 1 1 xin/ref
programmable cloc k generator 6 november 11, 2016 5P49V5923 datasheet reference clock input pins and selection the 5P49V5923 supports up to two clock inputs. one input supports a crystal between xin and xout. xin can also be driven from a single ended reference clock. xin can accept small amplitude signals like from tcxo or one channel of a differential clock. the second clock input (clkin, clkinb) is a fully differential input that only accepts a reference clock. the differential input accepts differential clocks from all the differential logic types and can also be driven from a single ended clock on one of the input pins. the clksel pin selects the in put clock between either xtal/ref or (clkin, clkinb). either clock input can be set as the primary clock. the primary clock designation is to establis h which is the main reference clock to the pll. the non-primary clock is designated as the secondary clock in case the primary clock goes absent and a backup is needed. see the previous page for more details about primary versus secondary clock operation. the two external reference clocks can be manually selected using the clksel pin. the sm bi ts must be set to ?0x? for manual switchover which is detailed in manual switchover mode section. crystal input (xin/ref) the crystal used should be a fundamental mode quartz crystal; overtone crystal s should not be used. a crystal manufacturer will calibrate its crystals to the nominal frequency with a certain load capacitance value. when the oscillator load capacitance matches the crystal load capacitance, the oscillation fr equency will be accurate. when the oscillator load capacitance is lower than the crystal load capacitance, the oscillation frequency will be higher than nominal and vice versa so for an accurate oscillation frequency you need to make sure to match the oscillator load capacitance with the crystal load capacitance. to set the oscillator load capa citance there are two tuning capacitors in the ic, one at xin and one at xout. they can be adjusted independently but commonly the same value is used for both capacitors. the value of each capacitor is composed of a fixed capacitance amount plus a variable capacitance amount set with the xtal[5:0] register. adjustment of the crystal tuning capacitors allows for maximum flexibility to accommod ate crystals from various manufacturers. the range of tuni ng capacitor values available are in accordance with the following table. xtal[5:0] tuning capacitor characteristics the capacitance at each crystal pin inside the chip starts at 9pf with setting 000000b and can be increased up to 25pf with setting 111111b. the step per bit is 0.5pf. you can write the following equation for this capacitance: ci = 9pf + 0.5pf xtal[5:0] the pcb where the ic and the crystal will be assembled adds some stray capacitance to each crystal pin and more capacitance can be added to each crystal pin with additional external capacitors. you can write the following equations for the total capacitance at each crystal pin: c xin = ci 1 + cs 1 + ce 1 c xout = ci 2 + cs 2 + ce 2 ci 1 and ci 2 are the internal, tunable capacitors. cs 1 and cs 2 are stray capacitances at each crystal pin and typical values are between 1pf and 3pf. ce 1 and ce 2 are additional external capacitors that can be added to increase the crystal load capacitance beyond the tuning range of the internal capacitors. however, increasing the load capaci tance reduces the oscillator gain so please consult the factory when adding ce 1 and/or ce 2 to avoid crystal startup issues. ce 1 and ce 2 can also be used to adjust for unpredictable stray capacitance in the pcb. the final load capacitance of the crystal: cl = c xin c xout / (c xin + c xout ) for most cases it is reco mmended to set the value for capacitors the same at each crystal pin: c xin = c xout = cx cl = cx / 2 the complete formula when the capacitance at both crystal pins is the same: cl = (9pf + 0.5pf xtal[5:0] + cs + ce) / 2 parameter bits step (p f) min (pf) max (pf) xtal 6 0.5 9 25 ?
november 11, 2016 7 progra mmable clock generator 5P49V5923 datasheet example 1 : the crystal load capacitan ce is specified as 8pf and the stray capacitance at each crystal pin is cs=1.5pf. assuming equal capacitance value at xin and xout, the equation is as follows: 8pf = (9pf + 0.5pf xtal[5:0] + 1.5pf) / 2 0.5pf xtal[5:0] = 5.5pf xtal[5:0] = 11 (decimal) example 2 : the crystal load capacitance is specified as 12pf and the stray capacitance cs is unknown. footprints for external capacitors ce are added and a worst case cs of 5pf is used. for now we use cs + ce = 5pf and the right value for ce can be determined later to make 5pf together with cs. 12pf = (9pf + 0.5pf xtal[5:0] + 5pf) / 2 xtal[5:0] = 20 (decimal) manual switchover mode when sm[1:0] is ?0 x?, the redundant inputs are in manual switchover mode. in this mode, clksel pin is used to switch between the primary and secondary clock sources. the primary and secondary clock source setting is determined by the primsrc bit. during the swit chover, no glitches will occur at the output of the device, al though there may be frequency and phase drift, depending on the exact phase and frequency relationship between the primary and secondary clocks.
programmable cloc k generator 8 november 11, 2016 5P49V5923 datasheet otp interface the 5P49V5923 can also store its configuration in an internal otp. the contents of the device's internal programming registers can be saved to the otp by setting burn_start (w114[3]) to high and can be loaded back to the internal programming registers by setting usr_rd_start(w114[0]) to high. to initiate a save or restore using i 2 c, only two bytes are transferred. the device address is issued with the read/write bit set to ?0?, followed by the appropriate command code. the save or restore instruction executes after the stop condition is issued by the master, during which time the 5P49V5923 will not generate acknowledge bits. the 5P49V5923 will acknowledge the instructions after it has completed execution of them. during that time, the i 2 c bus should be interpreted as busy by all other users of the bus. on power-up of the 5P49V5923, an automatic restore is performed to load the otp contents into the internal programming registers. the 5P49V5923 will be ready to accept a programming instruction once it acknowledges its 7-bit i 2 c address. availability of prim ary and secondary i 2 c addresses to allow programming for multiple devices in a system. the i 2 c slave address can be changed from the default 0xd4 to 0xd0 by programming the i2c_addr bit d0. versaclock 5 programming guide provides detailed i 2 c programming guidelines and register map. sd/oe pin function the polarity of the sd/oe signal pin can be programmed to be either active high or low with the sp bit (w16[1]). when sp is ?0? (default), the pin becomes active low and when sp is ?1?, the pin becomes active high. the sd/oe pin can be configured as either to shutdown the pll or to enable/disable the outputs. the sh bit controls the configuration of the sd/oe pin the sh bit needs to be high for sd/oe pin to be configured as sd . when configured as sd, device is shut down, and the single-ended lvcmos outputs are driven low. when configured as oe, and outputs are disabled, the outputs are driven high/low. table 5: sd/oe pin fu nction truth table output divides each output divide block has a synchronizing por pulse to provide startup alignment betw een outputs divides. this allows alignment of outputs fo r low skew performance. this low skew would also be realized between outputs that are both integer divides from the vco frequency. this phase alignment works when using configuration with sel1, sel0. for i 2 c programming, i 2 c reset is required. an output divide bypass mode (divide by 1) will also be provided, to allow multiple buffered reference outputs. each of the two output divides are comprised of a 12 bit integer counter, and a 24 bit fractional counter. the output divide can operate in integer divide only mode for improved performance, or utiliz e the fractional coun ters to generate a clock frequency accurate to 50 ppb. each of the output divides also have structures capable of independently generating spread spectrum modulation on the frequency output. the output divide also has the capability to apply a spread modulation to the output frequency. independent of output frequency, a triangle wave modulation between 30 and 63khz may be generated. for all outputs, there is a bypass mode, to allow the output to behave as a buffered copy of the input. sd/oe input sp sh oen osn global shutdown outn sh bit sp bit osn bit oen bit sd/oe outn 0 0 0 x x tri-state 2 0 0 1 0 x output active 0 0 1 1 0 output active 0 0 1 1 1 output driven high low 0 1 0 x x tri-state 2 0 1 1 0 x output active 0 1 1 1 0 output driven high low 0 1 1 1 1 output active 1 0 0 x 0 tri-state 2 1 0 1 0 0 output active 1 0 1 1 0 output active 1 1 0 x 0 tri-state 2 1 1 1 0 0 output active 1 1 1 1 0 output driven high low 1x x x 1 output driven high low 1 note 1 : global shutdown note 2 : tri-state regardless of oen bits
november 11, 2016 9 progra mmable clock generator 5P49V5923 datasheet output skew for outputs that share a common output divide value, there will be the ability to skew output s by quadrature values to minimize interaction on the pcb. the skew on each output can be adjusted from 0 to 360 degrees. skew is adjusted in units equal to 1/32 of the vco period. so, for 100 mhz output and a 2800 mhz vco, you can select how many 11.161ps units you want added to your skew (resulting in units of 0.402 degrees). for example, 0, 0.402, 0.804, 1.206, 1.408, and so on. the granularity of the skew adjustment is always dependent on the vco period and the output period. output drivers the operating voltage ranges of each output is determined by its independent output power pin (v ddo ) and thus each can have different output voltage leve ls. output voltage levels of 1.8v, 2.5v, or 3.3v are supported for lvcmos. each output may be enabled or disabled by register bits. when disabled an output will be in a logic 0 state as determined by the programming bit table shown on page 6. lvcmos operation outputs out1 & out2 each operate the frequency as determined by corresponding programmed fractional output dividers. all the previously described configuration and control apply equally to all outputs. frequency, phase alignment, voltage levels and en able / disable status apply to all the outx pins. the outputs can be selected to be phase-aligned with each other or inverted relative to one another by register programming bits. selection of phase-alignment may have negative effects on the phase noise performance of any part of the device due to increased simultaneous switching noise within the device. device hardware configuration the 5P49V5923 supports an internal one-time programmable (otp) memory that can be pre-programmed at the factory with up to 4 complete device configuration. these configurations can be over-written using the serial interface once reset is complete . any configuration written via the programming interface needs to be re-written after any power cycle or rese t. please contact idt if a specific factory-programmed configuration is desired. device start-up & reset behavior the 5P49V5923 has an internal power-up reset (por) circuit. the por circuit will remain acti ve for a maximum of 10ms after device power-up. upon internal por circuit expi ring, the device will exit reset and begin self-configuration. the device will load internal registers according to ta b l e 3 . once the full confi guration has been loaded, the device will respond to accesses on the serial port and will attempt to lock the pll to the selected source and begin operation. power up ramp sequence vdda and vddd must ramp up together. vddo0~2 must ramp up before, or concurrently with, vdda and vddd. all power supply pins must be connected to a power rail even if the output is unused. all power supplies must ramp in a linear fashion and ramp monotonically. vddo0~2 vdda vddd
programmable clock genera tor 10 november 11, 2016 5P49V5923 datasheet i 2 c mode operation the device acts as a slave device on the i 2 c bus using one of the two i 2 c addresses (0xd0 or 0xd4) to allow multiple devices to be used in the system. the interface accepts byte-oriented block write and block read operations. two address bytes specify the register address of the byte position of the first register to write or read. data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first). read and write block transfers can be stopped after any complete byte transfer. during a write operation, data will not be moved into the registers until the stop bit is received, at wh ich point, all data received in the block write will be wr itten simultaneously. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-down resistors ha ve a size of 100k ? typical. i 2 c slave read and write cycle sequencing current ? read s dev ? addr ? + ? r a data ? 0 a data ? 1 a a data ? n abar p sequential ? read s dev ? addr ? + ? w a data ? 0 a data ? 1 a a data ? n abar p reg ? start ? addr a sr dev ? addr ? + ? r a sequential ? write s dev ? addr ? + ? w a data ? 0 p a data ? 1 a a data ? n a from ? master ? to ? slave from ? slave ? to ? master reg ? start ? addr a s ? = ? start sr ? = ? repeated ? start a ? = ? acknowledge abar= ? none ? acknowledge p ? = ? stop
november 11, 2016 11 progra mmable clock generator 5P49V5923 datasheet table 6: i 2 c bus dc characteristics table 7: i 2 c bus ac characteristics note 1: a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. note 2: i2c inputs are 5v tolerant. symbol parameter conditions min typ max unit v ih input high level for sel1/sda pin and sel0/scl pin. 0.7xv ddd 5.5 2 v v il input low level for sel1/sda pin and sel0/scl pin. gnd-0.3 0.3xv ddd v v hys hysteresis of inputs 0.05xv ddd v i in input leakage current -1 30 a v ol output low voltage i ol = 3 ma 0.4 v symbol parameter min typ max unit f sclk serial clock frequency (scl) 10 400 khz t buf bus free time between stop and start 1.3 s t su:start setup time, start 0.6 s t hd:start hold time, start 0.6 s t su:data setup time, data input (sda) 0.1 s t hd:data hold time, data input (sda) 1 0s t ovd output data valid from clock 0.9 s c b capacitive load for each bus line 400 pf t r rise time, data and clock (sda, scl) 20 + 0.1xc b 300 ns t f fall time, data and clock (sda, scl) 20 + 0.1xc b 300 ns t high high time, clock (scl) 0.6 s t low low time, clock (scl) 1.3 s t su:stop setup time, stop 0.6 s
programmable clock genera tor 12 november 11, 2016 5P49V5923 datasheet table 8: absolute maximum ratings stresses above the ratings listed below can cause permanent dama ge to the 5P49V5923. these ratings, which are standard values f or idt commercially rated parts, are stress ratings only. functional oper ation of the device at these or any other conditions above th ose indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended peri ods can affect product reliability. electrical parameters are guarante ed only over the recommended operating temperature range. table 9: recommended operation conditions note: v ddo 1 and v ddo 2 must be powered on either before or simultaneously with v ddd , v dda and v ddo 0. item rating supply voltage, v dda, v ddd, v ddo 3.465v inputs xin/ref clkin, clkinb other inputs 0v to 1.2v voltage swing 0v to 1.2v voltage swing single-ended -0.5v to v ddd outputs, v ddo (lvcmos) -0.5v to v ddo + 0.5v outputs, i o (sda) 10ma package thermal impedance, ? ja 42 ? c/w (0 mps) package thermal impedance, ? jc 41.8 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c esd human body model 2000v junction temperature 125c symbol parameter min typ max unit v ddox power supply voltage for supporting 1.8v outputs 1.71 1.8 1.89 v v ddox power supply voltage for supporting 2.5v outputs 2.375 2.5 2.625 v v ddox power supply voltage for supporting 3.3v outputs 3.135 3.3 3.465 v v ddd power supply voltage fo r core logic functions 1.71 3.465 v v dda analog power supply voltage. use filtered analog power supply. 1.71 3.465 v t a operating temperature, ambient -40 +85 c c load_out maximum load capacitance (3.3v lvcmos only) 15 pf f in external reference crystal 140mhz external reference clock clkin, clkinb 1200 t pu power up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 5 ms
november 11, 2016 13 progra mmable clock generator 5P49V5923 datasheet table 10:input capaci tance, lvcmos outp ut impedance, and internal pull-down resistance (t a = +25 c) table 11:crystal characteristics note: typical crystal used is fox 603-25-150 . for different reference crystal options please go to www.foxonline.com . table 12:dc electrica l characteristics symbol parameter min typ max unit c in input capacitance (clkin, clki nb, clksel, sd/oe, sel1/sda, sel0/scl) 37pf pull-down resistor clksel, sd/oe, sel1/sda, se l0/scl, clkin, clkinb, out0_sel_i2cb 100 300 k ? r out lvcmos output driver impedance (v ddo = 1.8v, 2.5v, 3.3v) 17 ? xin/ref programmable input capacitance at xin/ref 08pf xout programmable input capacitance at xout 08pf parameter test conditions min typ max units mode of oscillation fundamental frequency 82540mhz equivalent series resistance (esr) 10 100 ? shunt capacitance 7pf load capacitance (c l ) @ <=25mhz 6 8 12 pf load capacitance (c l ) > 25m to 40m 68pf maximum crystal drive level 100 w symbol parameter test conditions min typ max unit iddcore 3 core supply current 100 mhz on all outputs, 25 mhz refclk 30 34 ma iddox output buffer supply curr ent lvcmos, 50 mhz, 3.3v v ddox, 1,2 1.single cmos driver active. 16 18 ma lvcmos, 50 mhz, 2.5v v ddox, 1,2 14 16 ma lvcmos, 50 mhz, 1.8v v ddox, 1,2 12 14 ma lvcmos, 200 mhz, 3.3v v ddox, 1,2 2.measured into a 5? 50 ohm trace with 2 pf load. 3. iddcore = idda + iddd, no loads. 36 42 ma lvcmos, 200 mhz, 2.5v v ddox, 1,2 27 32 ma lvcmos, 200 mhz, 1.8v v ddox, 1,2 16 19 ma iddpd core power down current sd asserted, i 2 c programming 10 14 ma
programmable clock genera tor 14 november 11, 2016 5P49V5923 datasheet table 13:electrical characteristics ? di fferential clock input parameters 1,2 (supply voltage v dda , v ddd , v ddo 0 = 3.3v 5%, 2.5v 5%, 1.8v 5%, ta = -40c to +85c) 1. guaranteed by design and characteri zation, not 100% tested in production. 2. slew rate measured through 75mv win dow centered around differential zero. table 14:dc electrical chara cteristics for 3.3v lvcmos (v ddo = 3.3v5%, ta = -40c to +85c) 1 1. see ?recommended operating conditions? table. symbol parameter test conditions min typ max unit v ih input high voltage?clkin, clkinb single-ended input 0.55 1.7 v v il input low voltage?clkin, clkinb single-ended input gnd - 0.3 0.4 v v swing input amplitude - clkin, clkinb peak to peak value, single-ended 200 1200 mv dv/dt input slew rate - clkin, cl kinb measured differentially 0.4 8 v/ns i il input leakage low current v in = gnd -5 5 a i ih input leakage high current v in = 1.7v 20 a d tin input duty cycle measurement from differential waveform 45 55 % symbol parameter test conditions min typ max unit v oh output high voltage i oh = -15ma 2.4 v ddo v v ol output low voltage i ol = 15ma 0.4 v i ozdd output leakage current (out1~2) tri-state outputs, v ddo = 3.465v 5a i ozdd output leakage current (out0) tri-state outputs, v ddo = 3.465v 30 a v ih input high voltage single -ended inputs - clksel, sd/oe 0.7xvddd v ddd + 0.3 v v il input low voltage single- ended inputs, clksel, sd/oe gnd - 0.3 0.3xvddd v v ih input high voltage single-ended input out0_sel_i2cb 2v ddo 0 + 0.3 v v il input low voltage single-ended input out0_sel_i2cb gnd - 0.3 0.4 v v ih input high voltage single -ended input - xin/ref 0.8 1.2 v v il input low voltage single- ended input - xin/ref gnd - 0.3 0.4 v t r/ t f input rise/fall time clksel, sd/oe, sel1/sda, sel0/scl 300 ns
november 11, 2016 15 progra mmable clock generator 5P49V5923 datasheet table 15:dc electrical character istics for 2.5v lvcmos (v ddo = 2.5v5%, ta = -40c to +85c) table 16:dc electrical charact eristics for 1.8v lvcmos (v ddo = 1.8v5%, ta = -40c to +85c) symbol parameter test conditions min typ max unit v oh output high voltage i oh = -12ma 0.7xv ddo v v ol output low voltage i ol = 12ma 0.4 v i ozdd output leakage current (out1~2) tri-state outputs, v ddo = 3.465v 5a i ozdd output leakage current (out0) tri-state outputs, v ddo = 3.465v 30 a v ih input high voltage single -ended inputs - clksel, sd/oe 0.7xvddd v ddd + 0.3 v v il input low voltage single- ended inputs, clksel, sd/oe gnd - 0.3 0.3xvddd v v ih input high voltage single-ended input out0_sel_i2cb 1.7 v ddo 0 + 0.3 v v il input low voltage single-ended input out0_sel_i2cb gnd - 0.3 0.4 v v ih input high voltage single -ended input - xin/ref 0.8 1.2 v v il input low voltage single- ended input - xin/ref gnd - 0.3 0.4 v t r/ t f input rise/fall time clksel, sd/oe, sel1/sda, sel0/scl 300 ns symbol parameter test conditions min typ max unit v oh output high voltage i oh = -8ma 0.7 xv ddo v ddo v v ol output low voltage i ol = 8ma 0.25 x v ddo v i ozdd output leakage current (out1~2) tri-state outputs, v ddo = 3.465v 5a i ozdd output leakage current (out0) tri-state outputs, v ddo = 3.465v 30 a v ih input high voltage single -ended inputs - clksel, sd/o 0.7 * v ddd v ddd + 0.3 v v il input low voltage single- ended inputs, clksel, sd/ol gnd - 0.3 0.3 * v ddd v v ih input high voltage single-ended input out0_sel_i2cb 0.65 * v ddo 0v ddo 0 + 0.3 v v il input low voltage single-ended input out0_sel_i2cb gnd - 0.3 0.4 v v ih input high voltage single -ended input - xin/ref 0.8 1.2 v v il input low voltage single- ended input - xin/ref gnd - 0.3 0.4 v t r/ t f input rise/fall time clksel, sd/oe, sel1/sda, sel0/scl 300 ns
programmable clock genera tor 16 november 11, 2016 5P49V5923 datasheet table 17:ac timing ele ctrical characteristics (v ddo = 3.3v+5% or 2.5v+5% or 1.8v 5%, ta = -40c to +85c) (spread spectrum generation = off) symbol parameter test conditions min. typ. max. units f in 1 input frequency input frequency limit (xin) 840mhz input frequency limit (ref) 1200mhz input frequency limit (clkin, clkinb) 1200mhz f out output frequency single ended clock output limit (lvcmos) 1200mhz f vco vco frequency vco operating frequency range 2600 2900 mhz f pfd pfd frequency pfd operating frequency range 1 1 150 mhz f bw loop bandwidth input frequency = 25mhz 0.06 0.9 mhz t2 input duty cycle duty cycle 45 50 55 % t3 5 output duty cycle measured at vdd/2, all outputs except reference output out0, vddox= 2.5v or 3.3v 45 50 55 % measured at vdd/2, all outputs except reference output out0, vddox=1.8v 40 50 60 % measured at vdd/2, reference output out0 (5mhz - 120mhz) with 50% duty cycle input 40 50 60 % measured at vdd/2, reference output out0 (150.1mhz - 200mhz) with 50% duty cycle input 30 50 70 % t4 2 slew rate, slew[1:0] = 00 single-ended 3.3v lvcmos output clock rise and fall time, 20% to 80% of vddo (output load = 5 pf) vddox=3.3v 1.0 2.2 v/ns slew rate, slew[1:0] = 01 1.2 2.3 v/ns slew rate, slew[1:0] = 10 1.3 2.4 v/ns slew rate, slew[1:0] = 11 1.7 2.7 v/ns slew rate, slew[1:0] = 00 single-ended 2.5v lvcmos output clock rise and fall time, 20% to 80% of vddo (output load = 5 pf) vddox=2.5v 0.6 0.3 v/ns slew rate, slew[1:0] = 01 0.7 1.4 v/ns slew rate, slew[1:0] = 10 0.6 1.4 v/ns slew rate, slew[1:0] = 11 1.0 1.7 v/ns slew rate, slew[1:0] = 00 single-ended 1.8v lvcmos output clock rise and fall time, 20% to 80% of vddo (output load = 5 pf) vddox=1.8v 0.3 0.7 v/ns slew rate, slew[1:0] = 01 0.4 0.8 v/ns slew rate, slew[1:0] = 10 0.4 0.9 v/ns slew rate, slew[1:0] = 11 0.7 1.2 v/ns
november 11, 2016 17 progra mmable clock generator 5P49V5923 datasheet table 18:spread spectrum ge neration specifications t6 clock jitter cycle-to-cycle jitter (peak-to-peak), multiple output frequencies switch ing, lvcmos outputs (1.8 to 3.3v nominal output voltage) out0=25mhz out1=100mhz out2=125mhz 74 ps rms phase jitter (12khz to 5mhz integration range) reference clock (out0), 25 mhz lvcmos outputs (1.8 to 3.3v nominal output voltage). out0=25mhz out1=100mhz out2=125mhz 0.5 ps rms phase jitter (12khz to 20mhz integration range) lvcmos output, vddo = 3.465v, 25mhz crystal, 125mhz output frequency out0=25mhz out1=100mhz out2=125mhz 0.75 1.5 ps t7 output skew skew between the same frequencies, with outputs using the same driver format and phase delay set to 0ns. 75 ps t8 3 startup time pll lock time from power-up, measured after all vdd's have raised above 90% of their target value. 10 ms t9 4 startup time pll lock time from shutdown mode 34ms 1. practical lower frequency is dete rmined by loop filter settings. 2. a slew rate of 2.75v/ns or greater should be se lected for output frequenci es of 100mhz or higher. 3. includes loading the configuration bits from memory to pll re gisters. it does not include memory programming/write time. 4. actual pll lock time depends on the loop configuration. 5. duty cycle is only guaranteed at max slew rate settings. symbol parameter description min typ max unit f out output frequency output frequency range 5300mhz f mod mod frequency modulation frequency 30 to 63 khz f spread spread value amount of spread value (programmable) - center spread 0.25% to 2.5% %f out amount of spread value (programmable) - down spread -0.5% to -5% symbol parameter test conditions min. typ. max. units
programmable clock genera tor 18 november 11, 2016 5P49V5923 datasheet test circuits and loads test circuits and loads for outputs typical phase noise at 100mhz (3.3v, 25c) note : all outputs operational at 100mhz , phase noise plot with spurs on. outx v dda clk out gnd c l 0.1f v ddox 0.1f v ddd 0.1f
november 11, 2016 19 progra mmable clock generator 5P49V5923 datasheet 5P49V5923 applications schematic 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 d d c c b b a a layout notes. by 3 x the trace width. 2.do not share crystal load components. capacitor ground via with other bulk capacitor pad then through 3.route power from bead through clock chip vdd pad. 0.1uf capacitor pad then to 4.do not share ground vias. one ground pin one ground via. 1.separate xout and xin traces revision history 0.1 9/19/2014 first publication manufacture part number z@100mhz pkgsz dc res. current(ma) fair -rite 2504021217y0 120 0402 0.5 200 murata blm15ag221sn1 220 0402 0.35 300 murata blm15bb121sn1 120 0402 0.35 300 tdk mmz1005s241a 240 0402 0.18 200 tecs tar tb4532153121 120 0402 0.3 300 note:ferrite bead fb1 = place near i2c controller if used lvds termination 3.3v lvpecl termination hcsl termination configuration pull-up for hardware control remove for i2c lvcmos termination for lvds, lvpecl ac couple use termination on right 6,7,8,9 and 24 pull-down resistors: load capacitors use internal crystal for clkin for clkin for clkin have weak internal the following pins c3 is for pin 5 bais network is required 0.1 integrated device technology a 11 friday, september 19, 2014 5P49V5923a_sch san jose, ca size document number rev date: sheet of fg_x1 v1p8vca out_0_sel-i2c v1p8vc clkin v1p8vc clkinb outr0 clksel v1p8vc outr1 sda scl v1p8vc outr2 sd sda scl clkin out_0_sel-i2c clkinb v1p8vca outr2 out_2 fg_x2 v1p8vc v1p8vca vcc1p8 v3p3 v1p8vc u3 receiver 1 2 c12 .1uf 1 2 r12 50 1 2 r14 33 1 2 r11 50 1 2 r5 49.9 1% 1 2 c5 .1uf 1 2 c2 1uf 1 2 u4 receiver 1 2 u1 5P49V5923a 3 4 1 2 6 8 9 7 5 22 23 24 21 20 19 18 17 16 15 14 13 10 11 12 25 26 27 28 29 30 31 32 33 xout xin/ref clkin clkinb clksel sel1/sda sel0/scl sd/oe vdda vddd vddo0 out0_sel_i2cb vddo1 out1 nc vddo2 out2 nc vdda nc nc vdda nc nc epad epad epad epad epad epad epad epad epad c3 .1uf 1 2 c13 .1uf 1 2 c6 6.8 pf no-pop 1 2 r13 33 1 2 c1 10uf 1 2 c4 .1uf 1 2 r10 50 1 2 r15 33 1 2 fb1 signal_bead 1 2 r4 49.9 1% 1 2 r9 10k 1 2 r3 100 1 2 u2 receiver 1 2 c8 .1uf 1 2 r6 33 1 2 c9 .1uf 1 2 c7 6.8 pf no-pop 1 2 r7 10k 1 2 r8 10k 1 2 r2 2.2 1 2 gnd gnd y2 crystal_smd 4 1 2 3 25.000mhz cl=8pf
programmable clock genera tor 20 november 11, 2016 5P49V5923 datasheet overdriving the xin/ref interface lvcmos driver the xin/ref input can be overdr iven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xout pin can be left floating. the amplitude of the input signal should be between 500mv and 1.2v and the slew rate should not be less than 0.2v/ns. figure general diagram for lvcmos driver to xtal input interface shows an example of the interface diagram for a lvcmos driver. this configuration has three properties; the total output impedance of ro and rs matches the 50 ohm transmission line impedance, the vrx voltage is generated at the clkin inputs which maintains the lv cmos driver voltage level across the transmission line for best s/n and the r1-r2 voltage divider values ensure that the clock level at xin is less than the maximum value of 1.2v. general diagram for lvcmos driver to xtal input interface table 19 nominal voltage divider values vs lvcmos vdd for xin shows resistor values that ensure the maximum drive level for the xin/ref port is no t exceeded for all combinations of 5% tolerance on the driver vdd, the versaclock vdda and 5% resistor toleranc es. the values of the resistors can be adjusted to reduce the loading for slower and weaker lvcmos driver by increasing the voltage divider attenuation as long as the minimum drive level is maintained over all tolerances. to assist this as sessment, the total load on the driver is included in the table. table 19: nominal voltage divide r values vs lvcmos vdd for xin ? xout xin / ref r1 r2 c3 0. 1 uf v_ xin lv cmos vdd ro ro + rs = 50 o hms rs zo = 50 ohm lvcmos driver vdd ro+rs r1 r2 v_xin (peak) ro+rs+r1+r2 3.3 50.0 130 75 0.97 255 2.5 50.0 100 100 1.00 250 1.8 50.0 62 130 0.97 242
november 11, 2016 21 progra mmable clock generator 5P49V5923 datasheet wiring the differential input to accept single-ended levels figure recommended schematic for wiring a differential input to accept single-ended levels shows how a differential input can be wired to accept single ended levels. this configuration has three properties; the total output impedance of ro and rs matches the 50 ohm transmission line impedance, the vrx voltage is generated at the clkin inputs which maintains the lvcmos driv er voltage level across the transmission line fo r best s/n and the r1-r2 voltage divider values ensure that vrx p-p at clkin is less than the maximum value of 1.2v. recommended schematic for wiring a differential input to accept single-ended levels table 20 nominal voltage divider values vs driver vdd shows resistor values that ensu re the maximum drive level for the clkin port is not exceeded for all combinations of 5% tolerance on the driver vdd, the versaclock vddo_0 and 5% resistor tolerances . the values of the resistors can be adjusted to reduce the loading for slower and weaker lvcmos driver by increasing the impedance of the r1-r2 divider. to assist this assessmen t, the total load on the driver is included in the table. table 20: nominal voltage di vider values vs driver vdd hcsl differential clock input interface clkin/clkinb will accept dc coupled hcsl signals. clkin, clkinb input driven by an hcsl driver ? r1 r2 vrx versaclock 5 receiver clki n clki nb lv cmos vdd zo = 50 ohm ro + rs = 5 0 rs ro lvcmos driver vdd ro+rs r1 r2 vrx (peak) ro+rs+r1+r2 3.3 50.0 130 75 0.97 255 2.5 50.0 100 100 1.00 250 1.8 50.0 62 130 0.97 242 zo=50ohm zo=50ohm clkin clkinb versaclock 5 receiver q nq
programmable clock genera tor 22 november 11, 2016 5P49V5923 datasheet 3.3v differential lvpecl clock input interface the logic levels of 3.3v l vpecl and lvds can exceed vih max for the clkin/b pins. theref ore the lvpecl levels must be ac coupled to the versaclock differential input and the dc bias restored with external voltage dividers. a single table of bias resistor values is prov ided below for both for 3.3v lvpecl and lvds. vbias can be vddd, v ddox or any other available voltage at the versaclock receiver that is most conveniently access ible in layout. clkin, clkinb input driven by a 3.3v lvpecl driver clkin, clkinb input driven by an lvds driver table 21: bias resistors for 3.3v lv pecl and lvds drive to clkin/b +3.3v lvpecl driver zo=50ohm zo=50ohm versaclock 5 receiver r9 r10 50ohm 50ohm vbias rpu1 rpu2 clkin clkinb rtt 50ohm c5 0.01f c6 0.01f r15 4.7kohm r13 4.7kohm vbias (v) rpu1/2 (kohm) clkin/b bias voltage (v) 3.3 22 0.58 2.5 15 0.60 1.8 10 0.58 lvds driver zo=50ohm zo=50ohm versaclock 5 receiver rterm 100ohm vbias rpu1 rpu2 clkin clkinb c1 0.1f c2 0.1f r1 4.7kohm r2 4.7kohm
november 11, 2016 23 progra mmable clock generator 5P49V5923 datasheet 2.5v differential lvpecl clock input interface the maximum dc 2.5v lvpecl voltage meets the vih max clkin requirement. therefore, 2.5v lvpecl can be connected directly to the clki n terminals with out ac coupling clkin, clkinb input driven by a 2.5v lvpecl driver +2.5v lvpecl driver zo=50ohm zo=50ohm r1 r2 50ohm 50ohm rtt 18ohm versaclock 5 receiver clkin clkinb
programmable clock genera tor 24 november 11, 2016 5P49V5923 datasheet package outline and package dimensions (24-pin 4mm x 4mm vfqfpn) www.idt.com t i d
november 11, 2016 25 progra mmable clock generator 5P49V5923 datasheet package outline and pack age dimensions, cont. (24-pin 4mm x 4mm vfqfpn) www.idt.com t i d
programmable clock genera tor 26 november 11, 2016 5P49V5923 datasheet marking diagram 1. line 1 is the truncated part number. 2. ?ddd? denotes dash code. 3. ?yww? is the last digit of the year and week that the part was assembled. 4. ? ** ? denotes lot number. 5. ?$? denotes mark code. ordering information ?g? after the two-letter package code denote s pb-free configuration, rohs compliant. revision history part / order number shipping packaging package temperature 5P49V5923bdddnlgi tubes 24-pin vfqfpn -40 to +85c 5P49V5923bdddnlgi8 tape and reel 24-pin vfqfpn -40 to +85c rev. date originator description of change a 12/04/14 b. chandhoke initial release. b 07/13/15 b. chandhoke 1. added conditions text and min/max values for vih/vil. 2. updated 1.8v, 2.5v, and 3.3v vih/vil conditions text and min/max values for "single-ended inputs - clksel, sd/oe" 3. changed name of parameter "lock time" to "startup time" 4. added idt and fox crystal references. c 10/15/15 b. chandhoke changed device revision from ?a? to ?b?. d 11/12/15 b. chandhoke updated fvco, t3, and t4 parameters in ac characteristics table. e 09/19/16 y. guo corrected typo [ci1 to cs1] on page 6. f 10/19/16 y. guo removed idt crystal part number g 11/11/16 y. guo corrected typo for the order of t4 slew rates 5923b ddd yww**$
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications d escribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfun ction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2014 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales tech support www.idt.com/go/support

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